View NCP1632DR2G_8934541.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? semiconductor components industries, llc, 2017 july, 2017 ? rev. 0 1 publication order number: ncp1632/d ncp1632 interleaved, 2-phase power factor controller the ncp1632 integrates a dual mosfet driver for interleaved pfc applications. interleaving consists of paralleling two small stages in lieu of a bigger one, more difficult to design. this approach has several merits like the ease of implementation, the use of smaller components or a better distribution of the heating. also, interleaving extends the power range of critical conduction mode that is an efficient and cost ? effective technique (no need for low t rr diodes). in addition, the ncp1632 drivers are 180 phase shifted for a significantly reduced current ripple. housed in a soic16 package, the circuit incorporates all the features necessary for building robust and compact interleaved pfc stages, with a minimum of external components. general features ? near ? unity power factor ? substantial 180 phase shift in all conditions including transient phases ? frequency clamped critical conduction mode ( fccrm ) i.e., fixed frequency, discontinuous conduction mode operation with critical conduction achievable in most stressful conditions ? fccrm operation optimizes the pfc stage efficiency over the load range ? out ? of ? phase control for low emi and a reduced rms current in the bulk capacitor ? frequency fold ? back at low power to further improve the light load efficiency ? accurate zero current detection by auxiliary winding for valley turn on ? fast line / load transient compensation ? high drive capability: ? 500 ma / +800 ma ? signal to indicate that the pfc is ready for operation (?pfcok? pin) ? v cc range: from 10 v to 20 v safety features ? output over and under voltage protection ? brown ? out detection with a 500 ? ms delay to help meet hold ? up time specifications ? soft ? start for smooth start ? up operation ? programmable adjustment of the maximum power ? over current limitation ? detection of inrush currents typical applications ? computer power supplies ? lcd / plasma flat panels ? all off line appliances requiring power factor correction soic ? 16 d suffix case 751b device package shipping ? ordering information NCP1632DR2G soic ? 16 (pb ? free) 2500 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd801 1/d. pin assignment (top view) zcd1 ref5v/pfcok drv1 gnd vcc drv2 latch cs zcd2 fb rt osc vcontrol ffold bo ovp / uvp 1 marking diagram ncp1632g awlyww a = assembly location wl = wafer lot y = year ww = work week g = pb ? free package www. onsemi.com
ncp1632 www. onsemi.com 2 figure 1. typical application schematic emi filter ac line d r c 1 2 3 4 13 16 14 15 5 6 7 8 9 12 10 11 pfcok r ocp r zcd1 r zcd2 2 bulk l 2 l 1 m 1 m 2 d c ff c comp2 r comp1 c comp1 r t r fold r out3 r out1 r ovp1 r ovp3 r bo2 r bo3 c bo2 ovp in ovp in cs c fold r osc c osc c in v in v out d bypass v out r bo1 r ovp2 r out2 v cc v aux2 v aux2 c pfcok c vcc drv1 gnd drv2 pfcok latch cs zcd1 zcd2 ffold fb osc vcontrol rt bo ovp/uvp 1 table 1. maximum ratings symbol rating pin value unit v cc(max) i cc(max) maximum power supply v oltage continuous maximum current for v cc pin 11 ? 0.3, +20 100 v ma v max i max maximum input voltage on low power pins maximum current 1, 2, 3, 4, 6, 7, 8, 9, 10, 15, and 16 ? 0.3, +9.0 100 v ma v control(max) v control pin maximum input v oltage 5 ? 0.3, v control(clamp) (note 1) v p d r j ? a power dissipation and thermal characteristics maximum power dissipation @ t a = 70 c thermal resistance junction ? to ? air 550 145 mw c/w t j operating junction temperature range ? 40 to +125 c t j(max) maximum junction t emperature 150 c t s(max) storage temperature range ? 65 to +150 c t l(max) lead temperature (soldering, 10s) 300 c esd capability, hbm model (note 2) 2 kv esd capability, machine model (note 2) 200 v esd capability, charged device model (note 2) 1000 v stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be af fected. 1. ?v control(clamp) ? is the pin5 clamp voltage. 2. this device(s) contains esd protection and exceeds the following tests: human body model 2000 v per jedec standard jesd22 ? a114e machine model method 200 v per jedec standard jesd22 ? a115 ? a charged device model method 1000 v per jedec standard jesd22 ? c101e 3. this device contains latch ? up protection and exceeds 100 ma per jedec standard jesd78.
ncp1632 www. onsemi.com 3 table 2. typical electrical characteristics table (conditions: v cc = 15 v, v pin7 = 2 v, v pin10 = 0 v, t j from ? 25 c, to +125 c, unless otherwise specified) characteristics test conditions symbol min typ max unit startup and supply circuits supply v oltage startup threshold minimum operating v oltage hysteresis v cc(on) ? v cc(off) internal logic reset v cc increasing v cc decreasing v cc decreasing v cc(on) v cc(off) v cc(hyst) v cc(reset) 11 9.4 1.5 4.0 12 10 2.0 6.0 13 10.4 ? 7.5 v startup current v cc = 9.4 v i cc(start) ? 50 100 a supply current device enabled/no output load on pin6 current that discharges v cc in latch mode current that discharges v cc in off mode skip mode consumption f sw = 130 khz (note 4) v cc = 15 v, v pin10 = 5 v v cc = 15 v, pin 7 grounded v fb = 3 v i cc1 i cc(latch) i cc(off) i cc(skip) ? ? ? ? 3.5 0.4 0.4 ? 7.0 0.8 0.8 2.1 ma oscillator and frequency foldback charge current pin 6 open i ch 126 140 154 a maximum discharge current pin 6 open i disch 94.5 105 115.5 a i ffold over i cs ratio i cs = 30 a r ffold30 ? 1 ? pin 6 source current i cs = 30 a i ffold30 28 30 32 a oscillator upper threshold v osc(high) ? 5 ? v oscillator lower threshold v ffold = 4.2 v, v ffold falling v ffold = 3.8 v, v ffold falling v ffold = 3.8 v, v ffold rising v ffold = 2.0 v, v ffold falling v ffold = 0.8 v, v ffold falling v osc(low) 3.6 3.6 2.7 1.8 0.8 4.0 4.0 3.0 2.0 1.0 4.4 4.4 3.3 2.2 1.1 v oscillator swing (note 5) v ffold = 4.2 v, v ffold falling v ffold = 3.8 v, v ffold falling v ffold = 3.8 v, v ffold rising v ffold = 2.0 v, v ffold falling v ffold = 0.8 v, v ffold falling v osc(swing) 0.90 0.90 1.90 2.85 3.80 1.00 1.00 2.00 3.00 4.00 1.05 1.05 2.10 3.15 4.20 v current sense current sense voltage of fset i pin9 = 100 a i pin9 = 10 a v cs(th100) v cs(th10) ? 20 ? 10 0 0 20 10 mv current sense protection threshold t j = 25 c t j = ? 25 c to 125 c i ilim1 i ilim2 202 194 210 210 226 226 a threshold for in ? rush current detection i in ? rush 11 14 17 a gate drive drive resistance drv1 sink drv1 source drv2 sink drv2 source i pin14 = 100 ma i pin14 = ? 100 ma i pin11 = 100 ma i pin11 = ? 100 ma r snk1 r src1 r snk2 r src2 ? ? ? ? 7 15 7 15 15 25 15 25 product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 4. drv1 and drv2 pulsating at half this frequency, that is, 65 khz. 5. not tested. guaranteed by design. 6. not tested. guaranteed by design and characterization.
ncp1632 www. onsemi.com 4 table 2. typical electrical characteristics table (conditions: v cc = 15 v, v pin7 = 2 v, v pin10 = 0 v, t j from ? 25 c, to +125 c, unless otherwise specified) characteristics unit max typ min symbol test conditions gate drive drive current capability (note 5) drv1 sink drv1 source drv2 sink drv2 source v drv1 = 10 v v drv1 = 0 v v drv2 = 10 v v drv2 = 0 v i snk1 i src1 i snk2 i src2 ? ? ? ? 800 500 800 500 ? ? ? ? ma rise time drv1 drv2 c drv1 = 1 nf, v drv1 = 1 to 10 v c drv2 = 1 nf, v drv2 = 1 to 10 v t r1 t r2 ? ? 40 40 ? ? ns fall time drv1 drv2 c drv1 = 1 nf, v drv1 = 10 to 1 v c drv2 = 1 nf, v drv2 = 10 to 1 v t f1 t f2 ? ? 20 20 ? ? ns regulation block feedback voltage reference v ref 2.44 2.50 2.56 v error amplifier source current capability @ v pin2 = 2.4 v i ea(src) ? 20 a error amplifier sink current capability @ v pin2 = 2.6 v i ea(snk) +20 error amplifier gain g ea 115 200 285 s pin 5 source current when (v out(low) detect) is activated pfcok high pfcok low i control(boost) 175 55 220 70 265 85 a pin2 bias current v pin2 = 2.5 v i fb(bias) ? 500 500 na pin 5 v oltage: @ v pin2 = 2.4 v @ v pin2 = 2.6 v v control(clamp) v control(min) v control(range) ? ? 2.8 3.6 0.6 3 ? ? 3.5 v ratio (v out(low) detect threshold / v ref ) (note 5) fb falling v out(low) /v ref 95.0 95.5 96.0 % ratio (v out(low) detect hysteresis / v ref ) (note 5) fb rising h out(low) /v ref ? ? 0.5 % skip mode duty cycle v fb = 3 v d min ? ? 0 % ramp control (valid for the two phases) maximum drv1 and drv2 on ? time (fb pin grounded) v pin7 = 1.1 v, i pin3 = 50 a (note 5) v pin7 = 1.1 v, i pin3 = 200 a v pin7 = 2.2 v, i pin3 = 100 a v pin7 = 2.2 v, i pin3 = 400 a t on1 t on2 t on3 t on4 14.5 1.10 4.00 0.34 19.5 1.35 5.00 0.41 22.5 1.60 6.00 0.50 s pin 3 voltage v bo = v pin7 = 1.1 v, i pin3 = 50 a v bo = v pin7 = 1.1 v, i pin3 = 200 a v bo = v pin7 = 2.2 v, i pin3 = 50 a v bo = v pin7 = 2.2 v, i pin3 = 200 a v rt1 v rt2 v rt3 v rt4 1.068 1.068 2.165 2.165 1.096 1.096 2.196 2.196 1.126 1.126 2.228 2.228 v maximum v ton voltage not tested v ton(max) 5 v pin 3 current capability i rt(max) 1 ? ? ma pin 3 sourced current below which the controller is off i rt(off) 7 a pin 3 current range not tested i rt(range) 20 1000 a product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 4. drv1 and drv2 pulsating at half this frequency, that is, 65 khz. 5. not tested. guaranteed by design. 6. not tested. guaranteed by design and characterization.
ncp1632 www. onsemi.com 5 table 2. typical electrical characteristics table (conditions: v cc = 15 v, v pin7 = 2 v, v pin10 = 0 v, t j from ? 25 c, to +125 c, unless otherwise specified) characteristics unit max typ min symbol test conditions zero voltage detection circuit (valid for zcd1 and zcd2) zcd threshold voltage v zcd increasing v zcd falling v zcd(th),h v zcd(th),l 0.40 0.20 0.50 0.25 0.60 0.30 v zcd hysteresis v zcd decreasing v zcd(hys) 0.25 v input clamp v oltage high state low state i pin1 = 5.0 ma i pin1 = ? 5.0 ma v zcd(high) v zcd(low) 10 ? 0.65 v internal input capacitance (note 5) c zcd ? 10 ? pf zcd watchdog delay t zcd 80 200 320 s brown ? out detection brown ? out comparator threshold v bo(th) 0.97 1.00 1.03 v brown ? out current source i bo 6 7 8 a brown ? out blanking time (note 5) t bo(blank) 380 500 620 ms brown ? out monitoring window (note 5) t bo(window) 38 50 62 ms pin 7 clamped voltage if v bo < v bo(th) during t bo(blank) i pin7 = ? 100 a v bo(clamp) ? 965 ? mv current capability of the bo clamp i bo(clamp) 100 ? ? a hysteresis v bo(th) ? v bo(clamp) i pin7 = ? 100 a v bo(hys) 10 35 60 mv current capability of the bo pin clamp pnp transistor i bo(pnp) 100 ? ? a pin bo voltage when clamped by the pnp i pin7 = ? 100 a v bo(pnp) 0.35 0.70 0.90 v over and under voltage protections over ? voltage protection threshold v ovp 2.425 2.500 2.575 v ratio (v ovp / v ref ) (note 6) v ovp /v ref 99.2 99.7 100.2 % ratio uvp threshold over v ref v uvp /v ref 8 12 16 % pin 8 bias current v pin8 = 2.5 v v pin8 = 0.3 v i ovp(bias) ? 500 ? 500 na latch input pin latch threshold for shutdown v latch 140 166 200 mv pin latch bias current v pin10 = 2.3 v i latch(bias) ? 500 ? 500 na pfcok / ref5v pin 15 voltage low state v pin7 = 0 v, i pin15 = 250 a v ref5v(low) ? 60 120 mv pin 15 voltage high state v pin7 = 0 v, i pin15 = 5 ma v ref5v(high) 4.7 5.0 5.3 v current capability i ref5v 5 10 ? ma thermal shutdown thermal shutdown threshold t shdn 130 140 150 c thermal shutdown hysteresis t shdn(hys) ? 50 ? c product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 4. drv1 and drv2 pulsating at half this frequency, that is, 65 khz. 5. not tested. guaranteed by design. 6. not tested. guaranteed by design and characterization.
ncp1632 www. onsemi.com 6 table 3. detailed pin description pin number name function 1 zcd2 this is the zero current detection pin for phase 2 of the interleaved pfc stage. it is designed to mon- itor the voltage of an auxiliary winding to detect the inductor core reset and the valley of the mos- fet drain source voltage 2 fb this pin receives the portion of the pfc stage output voltage for regulation. v fb is also monitored by the dynamic response enhancer (dre) which drastically speeds ? up the loop response when the output voltage drops below 95.5 % of the wished level. 3 r t the resistor placed between pin 3 and ground adjusts the maximum on ? time in both phases, and hence the maximum power that can be delivered by the pfc stage. 4 osc oscillator pin. the oscillator sets the maximum switching frequency, particularly in medium ? and light ? load conditions when frequency foldback is engaged. 5 v control the error amplifier output is available on this pin for loop compensation. the capacitors and resistor connected between this pin and ground adjusts the regulation loop bandwidth that is typically set below 20 hz to achieve high power factor ratios. pin5 is grounded when the circuit is off so that when it starts operation, the power increases gradually (soft ? start). 6 ffold (freq. foldback) this pin sources a current proportional to the input current. placing a resistor and a capacitor be- tween the ffold pin and gnd, we obtain the voltage representative of the line current magnitude necessary to control the frequency foldback characteristics. 7 bo (brown ? out protection) apply an averaged portion of the input voltage to detect brown ? out conditions when v bo drops be- low 1 v. a 500 ? ms internal delay blanks short mains interruptions to help meet hold ? up time require- ments. when it detects a brown ? out condition, the circuit stops pulsing and grounds the ?pfcok? pin to disable the downstream converter. also an internal 7 ? a current source is activated to offer a programmable hysteresis. the pin2 voltage is internally re ? used for feed ? forward. ground pin 2 to disable the part. 8 ovp / uvp the circuit turns off when v pin 8 goes below v uvp (300 mv typically ? uvp protection) and disables the drive when the pin voltage exceeds v ovp (2.5 v typically ? ovp protection). 9 cs (current sense) the cs pin monitors a negative voltage proportional to the input current to limit the maximum current flowing in the phases. the ncp1632 also uses the cs information to prevent the pfc stage from starting operation in presence of large in ? rush currents. 10 latch apply a voltage higher than v stdwn (166 mv typically) to latch ? off the circuit. the device is reset by unplugging the pfc stage (practically when the circuit detects a brown ? out detection) or by forcing the circuit v cc below v cc rst (4 v typically). operation can then resume when the line is applied back. 11 drv2 this is the gate drive pin for phase 2 of the interleaved pfc stage. the high ? current capability of the totem pole gate drive (+0.5/ ? 0.8a) makes it suitable to effectively drive high gate charge power mosfets. 12 v cc this pin is the positive supply of the ic. the circuit starts to operate when v cc exceeds 12 v and turns off when v cc goes below 10 v (typical values). after start ? up, the operating range is 10.5 v up to 20 v. 13 gnd connect this pin to the pre ? converter ground. 14 drv1 this is the gate drive pin for phase 1 of the interleaved pfc stage. the high ? current capability of the totem pole gate drive (+0.5/ ? 0.8a) makes it suitable to effectively drive high gate charge power mosfets. 15 ref5v / pfcok the pin15 voltage is high (5 v typically) when the pfc stage is in a normal, steady state situation and low otherwise. this signal serves to ?inform? the downstream converter that the pfc stage is ready and that hence, it can start operation. 16 zcd1 this is the zero current detection pin for phase 1 of the interleaved pfc stage. it is designed to mon- itor the voltage of an auxiliary winding to detect the inductor core reset and the valley of the mos- fet drain source voltage
ncp1632 www. onsemi.com 7 figure 2. block diagram drv1 vdd regul vcc output buffer 1 tsd off uvlo fb vcontrol rt vton processing circuitry vton zcd2 gnd dt stdwn off pfcok / ref5v osc iref + ? v ovp off stdwn + ? error amplifier + ? 0.955*v dre comp +/-20 a freq foldback vcc 3v 4r r q s ref5v bo ovp v off ovlflag1 all the rs latches are reset dominant stup zcd1 latch ? off + ? + ? v uvp bo_nok vcc_ok regul pfcok 150 a vdd vref pfcok ovlflag1 lstup 5r oscillator low threshold control v osc(low) v zcd1 dt v dmg1 outon1 fault management ics > i ocp ics > i in ? rush current sense block (building of i proportional to i ) cs in + ? ics cs skip uvp in ? rush vcc < vccrst ovp drv2 output buffer 2 vcc r q s l pwm2 bo_nok brown ? out detection with 500 ? ms delay v zcd1 v dmg2 outon2 v lstdwn r q s off skip i ch ocp stop vpwm2 stop r q s l pwm1 vpwm1 stop clk1 clk2 v zcd1 v zcd2 q zcd1 q zcd2 clk1 clk2 vpwm1 vpwm2 drv1 drv2 in ? rush opamp v opamp v bo v bo v osc(low) 50 a v cc(on) / v cc(off) v ref ref uvp ovp v stdwn drv 1 drv 2 ilim1 in ? rush generation of the charge current for the internal timing capacitors (max on ? time setting for the twophases) zero current detection for phase 2 zero current detection for phase 1 on ? time control for the two phases internal thermal shutdown oscillator block with interleaving and frequency foldback
ncp1632 www. onsemi.com 8 detailed operating description introduction the ncp1632 is an interleaving, 2 ? phase pfc controller. it is designed to operate in critical conduction mode (crm) in heavy load conditions and in discontinuous conduction mode (dcm) with frequency foldback in light load for an optimized efficiency over the whole power range. in addition, the circuit incorporates protection features for a rugged operation. more generally, the ncp1632 functions make it the ideal candidate in systems where cost ? effectiveness, reliability, low stand ? by power, high ? level efficiency over the load range and near ? unity power factor are the key parameters: ? accurate and robust interleaving management : the ncp1632 modulates the oscillator swing as a function of the current cycle duration to control the delay between the two branches drive pulses. this on proprietary method is a simple but robust and stable solution to interleave the two branches. the 180 ? degree phase shift is ensured in all situations (including transient phases) and whatever the operation mode is (crm or dcm). ? frequency fold ? back and skip ? cycle capability for low power stand ? by : the ncp1632 optimizes the efficiency of your pfc stage over the whole load range. in medium ? and light ? load conditions, the switching frequency can linearly decay as a function of the line current magnitude (ffold mode) down to about 30 khz at very low power (depending on the osc pin capacitor). to prevent any risk of regulation loss at no load and to further minimize the consumed power, the circuit skips cycles when the error amplifier output reaches its low clamp level. ? fast line / load transient compensation : by essence, pfc stages are slow systems. thus, the output voltage of pfc stages may exhibit excessive over ? and under ? shoots because of abrupt load or input voltage variations (e.g. at start ? up). the ncp1632 incorporates a fast line / load compensation to avoid such large output voltage variations. practically, the circuit monitors the output voltage and: ? disables the drive to stop delivering power as long as the output voltage exceeds the over voltage protection (ovp) level. ? drastically speeds ? up the regulation loop (dynamic response enhancer) when the output voltage is below 95.5 % of its regulation level. this function is partly disabled during the startup phase to ensure a gradual increase of the power delivery (soft ? start). ? pfc ok : the circuit detects when the circuit is in normal situation or if on the contrary, it is in a start ? up or fault condition. in the first case, the pfcok pin is in high state and low otherwise. the pfcok pin serves to control the downstream converter operation in response to the pfc state. ? output stage totem pole : the ncp1632 incorporates a ? 0.5 a / +0.8 a gate driver to efficiently drive most to220 or to247 power mosfets. ? safety protections : the ncp1632 permanently monitors the input and output voltages, the inductor current and the die temperature to protect the system from possible over ? stresses and make the pfc stage extremely robust and reliable. in addition to the aforementioned ovp protection, one can list: ? maximum current limit : the circuit permanently senses the input current for over current protection and in ? rush currents detection, for preventing the excessive stress suffered by the mosfets if they turned on when large in ? rush currents take place. ? zero current detection : the ncp1632 prevents the mosfet from closing until the inductor current is zero, to ensure discontinuous conduction mode operation in each branch. ? under ? voltage protection : the circuit turns off when it detects that the output voltage goes below 12% of the ovp level (typically). this feature protects the pfc stage from starting operation in case of too low ac line conditions or in case of a failure in the ovp monitoring network (e.g., bad connection). ? brown ? out detection : the circuit detects too low ac line conditions and stop operating in this case. this protection protects the pfc stage from the excessive stress that could damage it in such conditions. ? thermal shutdown : an internal thermal circuitry disables the circuit gate drive and then keeps the power switch off when the junction temperature exceeds 150 c typically. the circuit resumes operation once the temperature drops below about 100 c (50 c hysteresis). interleaving an interleaved pfc converter consists of two paralleled pfc stages operated out ? of ? phase. each individual stage is generally termed phase, channel or branch. if the input current is well balanced, each phase processes half the total power. the size and cost of each individual branch is hence accordingly minimized and losses are spitted between the two channels. hence, hot spots are less likely to be encountered. also, if the interleaving solution requires more components, they are smaller and often more standard. in addition, they can more easily fit applications with specific form ? factors as required in thin flat panel tvs for instance.
ncp1632 www. onsemi.com 9 furthermore, if the two channels are properly operated out ? of ? phase, a large part of the switching ? frequency ripple currents generated by each individual branch cancel when they add within the emi filter and the bulk capacitors. as a result, emi filtering is significantly eased and the bulk capacitor rms current is drastically reduced. interleaving therefore extends the crm power range by sharing the task between the two phases and by allowing for a reduced input current ripple and a minimized bulk capacitor rms current. this is why this approach which at first glance, may appear more costly than the traditional 1 ? phase solution can actually be extremely cost ? effective and efficient for powers above 300 watts. and even less for applications like lcd and plasma tv applications where the need for smaller components, although more numerous, helps meet the required low ? profile form ? factors. figure 3. interleaved pfc stage emi filter load 1 2 3 413 16 14 15 5 6 7 89 12 10 11 () ltot i () d tot i 1 l i 1 d i 2 l i 2 d i in v out v bulk in i in c cc v sense 1 aux v 2 aux v acline ncp1631 load 1 2 3 413 16 14 15 5 6 7 89 12 10 11 branch 1 branch 2 () ltot i i 1 l i 1 d i 2 l i 2 d i v c in i v r 1 aux v 2 aux v ncp1631 ncp1632 i in i line the ncp1632 manages the 180 ? degree phase shift between the two branches by modulating the oscillator swing as a function of the current cycle duration in the inductor of each individual phase. this on proprietary technique ensures an accurate, stable and robust control of the delay between the two branches in all situations (including transient phases) and whatever the operation mode is (crm or dcm). the ncp1632 is a voltage mode controller. as a result, the input current is optimally shared between the two branches if they have an inductor of same value. if the inductances differ, out ? of ? phase operation will not be affected. simply, the branch embedding the lowest ? value inductor, will process more power as: p branch1 p branch2 l branch2 l branch1 (eq. 1) inductor typical deviation being below 5%, the power between 2 branches should not differ from more than 10%. provided its interleaving capability, the protections it features and the medium ? to light ? load efficiency enhancements it provides compared to traditional crm circuits, the ncp1632 is more than recommendable for powers up to 600 w with universal mains and up to 1 kw in narrow mains applications. ncp1632 on ? time modulation the ncp1632 incorporates an on ? time modulation circuitry to support both the critical and discontinuous conduction modes. figure 4 portrays the inductor current absorbed in one phase of the interleaved pfc stage. the initial inductor current of each switching cycle is always zero. the inductor current ramps up when the mosfet is on . the slope is ( v in / l ) where l is the inductor value. at the end of the on ? time ( t 1 ), the coil demagnetization phase starts. the current ramps down until it reaches zero. the duration of this phase is ( t 2 ). the system enters then the dead ? time ( t 3 ) that lasts until the next clock is generated. the ac line current is the averaged inductor current as the result of the emi filter ?polishing? action. hence, the line current produced by one of the phase is: i in v in t 1 (t 1 t 2 ) 2t l (eq. 2) where (t = t 1 + t 2 + t 3 ) is the switching period and v in is the ac line rectified voltage. figure 4. current cycle within a branch eq. 2 shows that the input current is proportional to the input voltage if () 11 2 tt t t ?? + ?? ?? ?? is a constant. this is what the ncp1632 does. using the ?vton processing block? of figure 5, the ncp1632 modulates t1 so that () 11 2 tt t t ?? + ?? ?? ?? remains a constant: t 1 (t 1 t 2 ) t c t v regul i t (eq. 3) where c t and i t respectively, are the capacitor and charge current of the internal ramp used to control the on ? time and
ncp1632 www. onsemi.com 10 v regul is the signal derived from the regulation block which adjusts the on ? time. this on semiconductor proprietary technique makes the ncp1632 able to support the frequency clamped critical conduction mode of operation, that is, to operate in discontinuous ? or in critical ? conduction mode according to the conditions, without degradation of the power factor. critical conduction mode is naturally obtained when the inductor current cycle is longer than the minimum period controlled by the oscillator. discontinuous conduction mode is obtained in the opposite situation. in this case, the switching frequency is clamped. hence, the averaged current absorbed by one of the phase of the pfc converter: i in(phase1) i in(phase2) v in 2l c t v regul i t (eq. 4) given the regulation low bandwidth of pfc systems, ( v control ) and then ( v regul ) are slow varying signals. hence, the line current absorbed by each phase is: i in(phase1) i in(phase2) k v in (eq. 5) where k is a constant ( ?? ? = ? ? ?? ?? 2 tregul t cv k li ). hence, the input current is then proportional to the input voltage and the ac line current is properly shaped. this analysis is valid for dcm but also crm which is just a particular case of this functioning where (t 3 = 0). as a result, the ncp1632 automatically adapts to the conditions and jumps from dcm and crm (and vice versa) without power factor degradation and without discontinuity in the power delivery. the total current absorbed by the two phases is then: i in(total) c t v regul l i t v in (eq. 6) this leads to the following line rms current and average input power: i in(rms) c t v regul l i t v in(rms) (eq. 7) p in(avg) c t v regul l i t v in(rms) 2 (eq. 8) feedforward: the c t timing capacitors (one per phase) are internal and are well matched for an optimal current balancing between the two branches of the interleaved converter. as detailed in the brown ? out section, the i t current is internally processed to be proportional to the square of the voltage applied to the bo pin (pin 7). since the bo pin is designed to receive a portion of the average input voltage, the i t current is proportional to the square of the line magnitude which provides feedforward. in a typical application, the bo pin voltage is hence: v pin7 22 v in(rms) r bo2 r bo1 r bo2 (eq. 9) where r bo 1 and r bo 2 are the scaling down resistors for bo sensing (see brown ? out section) in addition, i t is programmed by the pin 3 resistor so that the maximum on ? time obtained when v regul is max (1.66 v) is given by: t on,max ( s) 50 10 9 r t 2 v pin7 2 (eq. 10) from this, we can deduce the input current and power expressions: i in(rms) 62 10 14 r t 2 l v in(rms) 1 r bo1 r bo2 2 v regul v regul(max) (eq. 11) p in(avg) 62 10 14 r t 2 l 1 r bo1 r bo2 2 v regul v regul(max) (eq. 12) figure 5. v ton processing circuit + ? ? > v to n d u ring (t1+t2) ? > 0 v during t3 (dead ? time ) ? > v to n *(t1+t2)/t in average vton + ? timing capacitor saw ? to o th to pwm latch pwm comparator in 1 s1 s2 c1 r1 skip oa1 of f s3 ov p pfcok in ? ru s h 0.5* (i se nse ? 210 ) oc p v regul v bocomp (from bo block) dt (high during dead ? time)
ncp1632 www. onsemi.com 11 regulation block and low output voltage detection a trans ? conductance error amplifier with access to the inverting input and output is provided. it features a typical trans ? conductance gain of 200 s and a typical capability of 20 a. the output voltage of the pfc stage is typically scaled down by a resistors divider and monitored by the inverting input (feed ? back pin ? pin2). the bias current is minimized (less than 500 na) to allow the use of a high impedance feed ? back network. the output of the error amplifier is pinned out for external loop compensation (pin5). a type ? 2 compensator is generally applied between pin5 and ground, to set the regulation bandwidth in the range of 20 hz, as need in pfc applications (refer to application note and8407). the swing of the error amplifier output is limited within an accurate range: ? it is maintained above a lower value (v f ? 0.6 v typically) by the ?low clamp? circuitry. when this circuitry is activated, the power demand is minimum and the ncp1632 enters skip mode (the controller stops pulsating) until the clamp is no more active. ? it is clamped not to exceed 3.0 v + the same v f voltage drop. hence, v pin5 features a 3 v voltage swing. v pin5 is then offset down by (v f ) and divided by three before it connects to the ?v ton processing block? and the pwm section. finally, the output of the regulation is a signal (?v regul ? of the block diagram) that varies between 0 and 1.66 v. figure 6. regulation block figure 7. v regul versus v control v regul v control v f 3 v + v f 1.66 v + ? + ? 0.955*vref dynamic response enhancer e rr o r am p lifier off v control fb vref 20 a vout low detect pfcok 150 a 50 a v regul v f 3v 5r 4r v f provided the low bandwidth of the regulation loop, sharp variations of the load, may result in excessive over and under ? shoots. over ? shoots are limited by the over ? voltage protection (see ovp section). a dynamic response enhancer circuitry (dre) is embedded to contain the under ? shoots. practically, an internal comparator monitors the feed ? back signal ( v fb ) and connects a 200 a current source to speed ? up the charge of the compensation network when v fb is lower than 95.5% of its nominal value. finally, it is like if the comparator multiplied the error amplifier gain by about 10. one must note that a large part of the dre current source (150 a out of 200 a) cannot be enabled until the converter output voltage has reached its target level (that is when the ?pfcok? signal of the block diagram, is high). this is because, at the beginning of operation, it is generally welcome that the compensation network charges slowly and gradually for a soft start ? up. zero current detection while the on time is constant, the core reset time varies with the instantaneous input voltage. the ncp1632 detects the demagnetization completion by sensing the inductor voltage. sensing the voltage across the inductor allows an accurate zero current detection, more specifically, by detecting when the inductor voltage drops to zero. monitoring the inductor voltage is not an economical solution. instead, a smaller winding is taken off of the boost inductor. this winding (called the ?zero current detection? or zcd winding) gives a scaled version of the inductor voltage that is easily usable by the controller. furthermore, this zcd winding is coupled so that it exhibits a negative voltage during the mosfet conduction time (flyback configuration) as portrayed by figure 8. in that way, the zcd voltage (?v aux ?) falls and starts to ring around zero volts when the inductor current drops to
ncp1632 www. onsemi.com 12 zero. the ncp1632 detects this falling edge and prevents any new current cycle until it is detected. figure 8 shows how it is implemented. for each phase, a zcd comparator detects when the voltage of the zcd winding exceeds its upper threshold (0.5 v typically). when this is the case, the coil is in demagnetization phase and the latch l zcd is set. this latch is reset when the next driver pulse occurs. hence the output of this latch (q zcd ) is high during the whole off ? time (demagnetization time + any possible dead time). the output of the comparator is also inverted to form a signal which is and?d with the q zcd output so that the and gate output (v zcd ) turns high when the v aux voltage goes below zero (below the 0.25 v lower threshold of the zcd comparator to be more specific). as a result, the zcd circuitry detects the v aux falling edge. it is worth noting that as portrayed by figure 9, v aux is also representative of the mosfet drain ? source voltage (?v ds ?). more specifically, when v aux is below zero, v ds is minimal (below the input voltage v in ). that is why v zcd is used to enable the driver so that the mosfet turns on when its drain ? source voltage is low. valley switching reduces the losses and interference. l1 d1 cbulk m1 drv1 14 + ? 0.5 v zcd1 16 vcc output buffe r 1 200 ? s delay vin dt zcd2 1 l2 d2 vout cbulk m2 drv2 11 vcc vin vzcd2 + ? 0.5 v qzcd2 and1 vzcd1 set1 set2 in ? rush in ? rush figure 8. zero current detection rzcd2 rzcd1 negative and positive clamp v dmg1 l zcd qzcd1 q s r q s r q s r s r q q zcd v dmg2 off (from fault management block) clk2 (from phase management block) clk1 (from phase management block) s q r pwm latch ph1 pwm latch ph2 reset signal (from ph2 pwm comparator) reset signal (from ph1 pwm comparator) output buffe r 2 negative and positive clamp at startup or after an inactive period (because of a protection that has tripped for instance), there is no energy in the zcd winding and therefore no voltage signal to activate the zcd comparator. this means that the driver will never turn on. to avoid this, an internal watchdog timer is integrated into the controller. if the driver remains low for more than 200 s (typical), the timer sets the l zcd latch as the zcd winding signal would do. obviously, this 200 s delay acts as a minimum off ? time if there is no demagnetization winding voltage is detected. to prevent negative voltages on the zcd pins (zcd1 for phase 1 and zcd2 for phase 2), these pins are internally clamped to about 0 v when the voltage applied by the corresponding zcd winding is negative. similarly, the zcd pins are clamped to v zcd(high) (10 v typical), when the zcd voltage rises too high. because of these clamps, a resistor (r zcd1 and r zcd2 of figure 9) is necessary to limit the current from the zcd winding to the zcd pin. the clamps are designed to respectively source and sink 5 ma. it is hence recommended to dimension r zcd1 and r zcd2 to limit the zcd1 and zcd2 pins current below 5 ma.
ncp1632 www. onsemi.com 13 figure 9. zero current detection timing diagram (v aux is the voltage provided by the zcd winding) current sense the ncp1632 is designed to monitor a negative voltage proportional to the input current, i.e., the current drawn by the two interleaved branches ( i in ). as portrayed by figure 10, a current sense resistor ( r cs ) is practically inserted in the return path to generate a negative voltage ( v cs ) proportional to i in . figure 10. current sense block 9 cs negative clamp c in v in i cs current mirror i in i cs ocp m 1 c bulk v out drv 2 m 2 l 2 d 2 l 1 d 1 drv 1 v aux 2 v aux 1 in ? rush i cs r cs r ocp i in i cs emi filter i ilim 1 i in ? rush drv 2 drv 1 q zcd 2 q zcd 1 ( q zcd 1 and q zcd 2 are from the zcd block) ac line the ncp1632 uses v cs to detect when i in exceeds its maximum permissible level. to do so, as sketched by figure 11, the circuit incorporates an operational amplifier that sources the current necessary to maintain the cs pin
ncp1632 www. onsemi.com 14 voltage near zero. by inserting a resistor r ocp between the cs pin and r cs , we adjust the current that is sourced by the cs pin ( i cs ) as follows: r cs i in r ocp i cs 0 (eq. 13) which leads to: i cs r cs r ocp i in (eq. 14) in other words, the cs pin sources a current (i cs ) which is proportional to the input current. two functions use i cs : the over current protection and the in ? rush current detection. over ? curr ent protection (ocp) if i cs exceeds i ilim1 (210 a typical), an over ? current is detected and the on ? time is decreased proportionally to the difference between the sensed current i in and the 210 a ocp threshold. the on ? time reduction is done by injecting a current i neg in the negative input of the ?v ton processing circuit? opamp. (see figure 5) i neg i cs i ilim1 2 (eq. 15) this current is injected each time the ocp signal is high. the maximum coil current is: i in(max) r ocp r cs i ilim1 (eq. 16) in ? rush current detection when the pfc stage is plugged to the mains, the bulk capacitor is abruptly charged to the line voltage. the charge current (named in ? rush current) can be extremely huge particularly if no in ? rush limiting circuitry is implemented. the power switches should not turn on during this severe transient. if not, they may be over ? stressed and finally damaged. that is why, the ncp1632 permanently monitors the input current and delays the mosfet start of switching until (i in ) has vanished. this is the function of the i cs comparison to the i in ? rush threshold (14 a typical). when i cs exceeds i in ? rush , the comparator output (?in ? rush?) is high and prevents the pwm latches from setting (see block diagram). hence, the two drivers (drv1 and drv2) cannot turn high and the mosfets stay off. this is to guarantee that the mosfets remain open as long as if the input current exceeds 10% of the maximum current limit. again, this feature protects the mosfets from the possible excessive stress it could suffer from if it was allowed to turn on while a huge current flowed through the coil as it can be the case at start ? up or during an over ? load transient. the propagation delay ( i cs < i in ? rush ) to (drive outputs high) is in the range of few s. however when the circuit starts to operate, the ncp1632 disables this protection to avoid that the current produced by one phase and sensed by the circuit prevents the other branch from operating. practically, some logic grounds the in ? rush protection output when it detects the presence of ?normal current cycles?. this logic simply consists of the or combination of the drive and demagnetization signals as sketched by figure 10. over ? voltage protection while pfc circuits often use one single pin for both the over ? voltage protection (ovp) and the feed ? back, the ncp1632 dedicates one specific pin for the under ? voltage and over ? voltage protections. the ncp1632 configuration allows the implementation of two separate feed ? back networks (see figure 12): 1. one for regulation applied to pin 2. 2. another one for the ovp function (pin 8). figure 11. configuration with one feed ? back network for both ovp and regulation fb 1 2 3 4 13 16 14 15 5 6 7 12 10 11 ovp vout (bulk voltage) rout2 rout1 rout3 figure 12. configuration with two separate feed ? back networks fb 1 2 3 4 13 16 14 15 5 6 7 12 10 11 ovp vout (bulk voltage) rovp2 rout1 rout2 rovp1 9 8 9 8
ncp1632 www. onsemi.com 15 the double feed ? back configuration (figure 12) offers some up ? graded safety level as it protects the pfc stage even if there is a failure of one of the two feed ? back arrangements. in this case: the bulk regulation voltage (?v out(nom) ?) is: v out(nom) r out1 r out2 r out2 v ref (eq. 17) the ovp level (?v out(ovp) ?) is: v out(ovp) r ovp1 r ovp2 r ovp2 v ref (eq. 18) where v ref is the internal reference voltage (2.5 v typically) now, if wished, one single feed ? back arrangement is possible as portrayed by figure 11. the regulation and ovp blocks having the same reference voltage (v ref ), the resistance ratio r out2 over r out3 adjusts the ovp threshold. more specifically, the bulk regulation voltage (?v out(nom) ?) is: v out(nom) r out1 r out2 r out3 r out2 r out3 v ref (eq. 19) the ovp level (?v out(ovp) ?) is: v out(ovp) r out1 r out2 r out3 r out2 v ref (eq. 20) the ratio ovp level over regulation level is: v out(ovp) v out(nom) 1 r out3 r out2 (eq. 21) for instance, (v out(nom) = 105% ? v out(nom) ) leads to: (r out3 = 5% ? r out2 ). when the circuit detects that the output voltage exceeds the ovp level, it maintains the power switch open to stop the power delivery. oscillator section ? phase management the oscillator generates the clock signal that dictates the maximum switching frequency ( f osc ) of the interleaved pfc stage . in other words, each of the two interleaved branches cannot operate above half the oscillator frequency ( f osc /2). the oscillator frequency ( f osc ) is adjusted by the capacitor applied to osc pin (pin 4). typically, a 220 pf capacitor approximately leads to a 260 khz oscillator operating frequency, i.e., to a 130 khz clamp frequency for each branch. as shown by figure 13, a current source i ch (140 a typically) charges the osc pin capacitor until its voltage exceeds v osc ( high ) (5 v typically). at that moment, the oscillator enters a discharge phase for which i disch (105 a typ.) discharges the osc pin capacitor. this sequence lasts until v osc goes below the oscillator low threshold v oscl and a new charging phase starts*. an internal signal (? sync ? of figure 19) is high during the discharge phase. a divider by two uses the sync information to manage the phases of the interleaved pfc: the first sync pulse sets ?phase 1?, the second one, ?phase 2?, the third one phase 1 again ? etc. according to the selected phase, sync sets the relevant ?clock generator latch? that will generate the clock signal (? clk 1? for phase 1, ? clk 2? for phase 2) when sync drops to zero. actually, the drivers cannot turn on at this very moment if the inductor demagnetization is not complete. in this case, the clock signal is maintained high and the discharge time is prolonged although v osc is below v oscl , until when the core being reset, the drive pin turns high. the prolonged osc discharge ensures a substantial 180 ? degree phase shift in crm, out ? of ? phase operation being in essence, guaranteed in dcm. in the two conditions (crm or dcm), the interleaved operation is stable and robust. *as detailed in the following sections, v oscl is v osc(low) ? 4 v typically ? by default to set the frequency clamp level used in heavy ? load conditions. v oscl is varied between 1 and 3 v in ffold mode (frequency foldback mode) in response the ffold pin voltage.
ncp1632 www. onsemi.com 16 figure 13. ffold mode management osc i clk1 generation latch s q r clk1 drv1 c osc ch clk2 generation latch s q r clk2 drv2 divider by two phase1 i disch phase2 sync syncbar syncbar q_ph1 q_ph1 5 v syncbar osc latch s q r ffold 4 v 3v 1v + ? hfc mode ffold mode 4 v / 3 v i cs (from cs block) ffold mode 1 v and 3 v clamps control of the oscillator low threshold ( v oscl ) v oscl if a capacitor c osc is applied to the osc pin, the oscillator frequency is provided by: f osc 60 10 6 c osc (10 10 12 ) (eq. 22) and the switching frequency of each individual branch is clamped to the following f clamp : f clamp f osc 2 30 10 6 c osc (10 10 12 ) (eq. 23) recommended configuration as detailed above, the circuit automatically transitions between crm and dcm depending on the current cycle duration being longer or shorter than the clamp frequency set by the oscillator. however , these transitions can lead to small discontinuities of the line current. to avoid them, the circuit should be operated in crm without frequency ? clamp interference when the line current is high and in deep dcm when it is below a programmed level. deep dcm means that the switching frequency is low enough to ensure a significant dead ? time and prevent transitions between crm and dcm within the input voltage sinusoid. in figure 14 a) configuration, a single oscillator sets a frequency clamp. for instance, c osc = 220 pf forces 120 khz to be the maximum frequency within each branch (the ffold mode reduces this level in light load conditions). such a clamp value is likely to force dcm operation in part of the input voltage sinusoid. to be able to force full crm operation over a large working range, we would need to reduce c osc to a very low value (if not, the clamp frequency can be lower than the switching one leading to dcm operation near the line zero crossing in particular). still however, the oscillator must keep able to keep synchronized to the current cycle for proper out ? of ? phase control. this requires the oscillator swing to not to exceed its 1 v to 5 v range even in heavy load conditions when the switching frequency in each individual branch generally drops below 100 khz. this is generally not possible with a single small capacitor on the osc pin.
ncp1632 www. onsemi.com 17 figure 14. external components driving the osc pin c osc (e.g., 220 pf) osc pin r osc (e.g., 5.1 k ) c ff (e.g., 270 pf) c osc (e.g., 68 pf) osc pin r osc (e.g., 5.1 k ) c osc (e.g., 82 pf) c ff (e.g., 330 pf) osc pin a.) basic configuration a.) option 1 a.) option 2 instead, the schematic of either figure 14 b) or figure 14 c) is to be used where: ? c osc (which value is much less than the second capacitance c ff ) sets the high ? frequency operation necessary for operating in crm ? r osc limits the influence of the c ff capacitor as long as the oscillator swing remains below (r osc .i osc ) where i osc is the charge or discharge current depending on the sequence. the voltage across c osc being limited by r osc (to about 1 v with 5.1 k ), the second much ? higher ? value capacitor (c ff ) is engaged when heavy ? load crm operation imposes a larger oscillator swing. ? c ff sets the frequency in light load where the frequency foldback can force deep dcm operation (deep dcm means operation with a large dead ? time to be far from the zone where the circuit can transition from crm to dcm and vice versa). as previously mentioned, c ff also ensures that the oscillator voltage can stay above 1 v in deep crm conditions. finally, figure 14 b) and c) configurations provide some kind of variable ? capacitance oscillator. for instance, option b) provides the following typical characteristics: figure 15. clamp frequency in each individual branch with the configuration of figure 14 b) 300 khz frequency clamp in hfc mode (v ffold > 4 v) 1 vramp 396u 398u 400u 402u 404u time in seconds ? 1.00 1.00 3.00 5.00 7.00 vramp in volts plot1 1 . branch t s 33 v 5 v 4 1 vramp 392u 396u 400u 404u 408u time in seconds ? 1.00 1.00 3.00 5.00 7.00 vramp in volts plot1 1 . branch t s 136 v 5 v 3 1 vramp 360u 380u 400u 420u 440u time in seconds ? 1.00 1.00 3.00 5.00 7.00 vramp in volts plot1 1 branch t s 36 v 5 v 1 73 khz frequency clamp when entering ffold mode (v ffold = 3 v) 28 khz minimum frequency clamp (deepest dcm @ v ffold = 1 v)
ncp1632 www. onsemi.com 18 figure 16 illustrates the oscillator operation at a low ffold voltage. figure 16. operation at a low v ffold value (v ffold = 1.1 v) 9.50m 9.54m 9.58m 9.62m 9.66m time in seconds ? 1.00 1.00 3.00 5.00 7.00 1 2 3 4 5 6 7 8 9 i l1 i l2 v osc v ds1 v ds2 dcm / crmflag (high in dcm) 5 v v ffold is in the range of 1.1 v v ffold forces the osc valley ffold / hfc flag (high in ffold mode) hfc vs ffold modes the ncp1632 optimizes the pfc stage efficiency over the whole load range by entering the frequency foldback (ffold) mode when the line current magnitude is lower than a programmed level (see next section). more specifically, the circuit operates in: ? frequency foldback (ffold) mode when the line current magnitude is lower than a programmed level. in this mode, the circuit frequency clamp level is reduced as a function of the ffold pin voltage in order to reduce the frequency in medium ? and light ? load operation. the frequency can decrease down to about 30 khz at very low power (depending on the osc pin capacitor) ? high frequency clamp (hfc) mode when the line current is high. in this mode, the clamp level of the switching frequency is set high so that the pfc stage mostly runs in critical conduction mode which is more efficient than the discontinuous conduction mode in heavy load conditions. the transitions between the hfc and ffold modes and the frequency foldback characteristics are controlled by the ffold pin. frequency foldback (ffold) management as detailed in the ?current sense? section, the ncp1632 cs pin sources a current proportional to the input current ( i cs of figure 14). i cs is internally copied and sourced out of the ffold pin. this current is changed into a dc voltage by means of an external (r//c) network applied to the ffold pin. the obtained v ffold voltage is proportional to the line average current. as illustrated by figure 17, the pfc stage enters the frequency foldback mode (ffold mode) when v ffold goes below 3.0 v, and recovers high ? frequency clamp mode (hfc mode) when the ffold voltage exceeds 4 v.
ncp1632 www. onsemi.com 19 figure 17. frequency foldback control 9 emi filter ac line cs negative clamp current mirror i (i is proportional to the total input current) cs cs i cs i cs i in i in r cs r sense c in v in ffold 6 i cs pfc stage v out + ? hfc mode ffold mode 4 v / 3 v low ? pass filter to build a signal proportional to the average input current oscillator low threshold control in hfc mode, the oscillator lower threshold ( v oscl ) is fixed and equal to v osc ( low ) (4 v typically). in ffold mode, v oscl is modulated by the ffold pin voltage as follows: ? v oscl = v ffold if v ffold is between 1 and 3 v ? v oscl = 1 v if v ffold is below 1 v ? v oscl = 3 v if v ffold exceeds 3 v as an example, the ffold external resistor can be selected so that ( v ffold = 3 v) when the line current threshold is equal to 20% of the maximum current. in a 90 to 270 v rms application, above criterion leads the pfc stage to enter ffold mode at: ? 20% load at 90 v rms ? 60% load at 270 v rms the pfc stage will recover hfc mode ( v ffold = 4 v) at: ? 27% load at 90 v rms ? 81% load at 270 v rms above values assume a ripple ? free v ffold voltage. the power thresholds for transition can be shift and the hysteresis reduced by the v ffold ripple. at the transition between the two modes, the oscillator low threshold is 3 v. in the example of figure 15, this leads the branch clamp frequency to be 73 khz when entering and just before leaving the ffold mode. figure 18 shows a ?natural? transition ffold to hfc mode.
ncp1632 www. onsemi.com 20 figure 18. ?natural? transition ffold to hfc mode when v ffold exceeds 4 v 8.44m 8.48m 8.52m 8.56m 8.60m time in seconds ? 1.00 1.00 3.00 5.00 7.00 2 4 6 7 3 5 1 i l1 i l2 v osc v ds1 v ds2 dcm /crmflag (high in dcm) 5 v 3 v dcm operation crm operation v ffold exceeds the 4 v threshold ffold / hfc flag (high in ffold mode) hfc ? mode recovery the ffold pin sources a current proportional to the input current. placing a resistor and a capacitor between the ffold and gnd pins, we obtain the voltage representative of the line current magnitude necessary to control the frequency foldback characteristics. the ncp1632 naturally leaves the ffold mode operation when the sensed input current being large enough, the ffold pin voltage ( v ffold ) exceeds 4 v. such a ffold to hfc transition is shown by figure 18. figure 19. easing hfc ? mode recovery 2 r6 100k s r q q 3 5 hfc mode dre ovlflag1 (high when v fb < v ref ) now, the ffold pin is heavily filtered and this time constant may cause long v ffold settling phases. if while in very light ? load conditions, the load abruptly rises, the ffold pin time constant may dramatically delay the hfc ? mode recovery. as a result, during the ffold mode of operation, the pfc stage may run in dcm and may not be able to provide the full power. to solve this, the ncp1632 forces hfc operation whenever the dre comparator trips* and remains in hfc mode until the output voltage recovers its regulation level (that is when ovlflag 1 of figure 22 turns low). at that moment, the conduction mode is normally selected as a function of the ffold pin voltage. see figure 19. *the dy namic response enhancer (dre) comparator trips when the output voltage drops below 95.5% of its regulation level. skip mode of operation the circuit enters skip mode when the regulation block output ( v control ) drops to its 0.6 v lower clamp level. at very light load and low line conditions, on ? times can be short enough no to enter the low ? consumption skip mode. to prevent such an inefficient continuous operation from occurring, the ncp1632 forces a minimum on ? time which corresponds to 10% the maximum on ? time. this does not mean that the pfc stage will enter skip mode when the load is less than 10% of the full load (or even much more considering the necessary headroom in the max on ? time setting when selecting r t ). since, the ncp1632 reduces the switching frequency in light load (ffold mode), this minimum on ? time corresponds to
ncp1632 www. onsemi.com 21 much lower power levels, typically, in the range of 2% of the full power. figure 20. v control low clamp low clamp the circuit consumption is minimized (below 1 ma) for a skipping period of time. pfcok / ref5v signal the ncp1632 can communicate with the downstream converter. the signal ?pfcok/ref5v? is high (5 v) when the pfc stage is in nominal operation and low otherwise. more specifically, ?pfcok/ref5v? is low: ? whenever a major fault condition is detected which turns off the circuit, i.e.: ? incorrect feeding of the circuit (?uvlo? high). the uvlo signal turns high when v cc drops below v cc(off) (10 v typically) and remains high until v cc exceeds v cc(on) (12 v typically). ? excessive die temperature detected by the thermal shutdown. ? under ? voltage protection (?uvp? high) ? brown ? out situation (?bonok? high) ? latching ? off of the circuit by an external signal applied to pin 10 and exceeding 166 mv (?stdwn? of the block diagram turns high). ? too low the current sourced by the r t pin (?r t(open) ?) ? during the pfc stage start ? up, that is, until the output voltage reaches its regulation level. the start ? up phase is detected by the latch ?l stup ? of the block diagram. ?l stup ? is in high state when the circuit enters or recovers operation after one of above major faults and resets when the error amplifier stops charging its output capacitor, that is, when the output voltage of the pfc stage has reached its desired regulation level. at that moment, ?stup? falls down to indicate the end of the start ? up phase. finally, ?pfcok/ref5v? is high when the pfc output voltage is properly and safely regulated. ?pfcok/ref5v? should be used to allow operation of the downstream converter. brown ? out protection the brown ? out pin is designed to receive a portion of the input voltage ( v in ). as v in is a rectified sinusoid, a capacitor must be applied to the bo pin so that v bo is proportional to the average value of v in . figure 21. brown ? out block bo emi filter ac line feed ? forward circuitry circuitry for brown ? out detection r q s l 500 ? ms delay reset 50 ? ms delay reset bo_nok 1 v 7 a reset bo delay t vdd v in c in c bo r cs r bo2 r bo1 rt current mirror i bo i bo rt vbo vbo (bo pin voltage) i charges the timing capacitor for both phases bo 980 mv v bo ? comp (high when v bo < 1 v) this pnp transistor maintains the bo pin below the bo threshold when the circuit is not fed enough to control the state of the bo block bo ? comp s 2 s 1 i bo 2 charges the timing capacitor for both phases of the interleaved pfc feed ? forward circuitry circuitry for brown ? out detection vbo
ncp1632 www. onsemi.com 22 the bo pin voltage is used by two functions (refer to figure 21): ? feedforward. generation of an internal current proportional to the input voltage average value (i rt ). v bo is buffered and made available on the r t pin (pin 3). hence, placing a resistor between pin 3 and ground, enables to adjust a current proportional to the average input voltage. this current (i rt ) is internally copied and squared to form the charge current for the internal timing capacitor of each phase. since this current is proportional to the square of the line magnitude, the conduction time is made inversely proportional to the line magnitude. this feed ? forward feature makes the transfer function and the power delivery independent of the ac line level. only the regulation output (v regul ) controls the power amount. note that if the i rt current is too low (below 7 a typically), the controller goes in off mode to avoid damaging the mosfets with too long conduction time. in particular, this addresses the case when the r t pin is open. ? brown ? out protection. a 7 a current source lowers the bo pin voltage when a brown ? out condition is detected. this is for hysteresis purpose as required by this function. in traditional applications, the monitored voltage can be very different depending on the phase: ? before operation, the pfc stage is off and the input bridge acts as a peak detector (refer to figure 22). as a consequence, the input voltage is approximately flat and nearly equates the ac line amplitude: () =? , 2 in in rms vt v , where v in , rms is the rms voltage of the line. hence, the voltage applied to the bo pin (pin 7) is: =? ? + 2 , 12 2 bo bo in rms bo bo r vv rr . ? after the pfc stage has started operation, the input voltage becomes a rectified sinusoid and the voltage applied to pin7 is: ? =? + , 2 12 22 in rms bo bo bo bo v r v rr , i.e., about 64% of the previous value. therefore, the same line magnitude leads to a v bo voltage which is 36% lower when the pfc is working than when it is off. that is why a large hysteresis (in the range of 50% of the upper threshold) is required. other applications may require a different hysteresis amount. that is why the hysteresis is made programmable and dependent on the internal 7 a current source. more specifically, re ? using the components of figure 21: ? the line upper bo threshold is: () () ?? +?? =? + ?? ?? + ?? 12 12 , 212 1 2 bo bo bo bo bo in rms bo th boh bo bo bo rr rri vv rrr where v bo ( th ) is the bo comparator threshold (1 v typically) and i bo , the 7 a current source. ? the line lower threshold is: () () + =? ? 12 , 2 22 bo bo in rms bo th bol bo rr vv r hence the ratio upper over lower threshold is: () () () ?? ?? ?? =?+ ?? +? ?? , 12 12 () , 2 1 in rms boh bo bo bo bo bo bo th in rms bol v rr i rrv v as in general r bo1 is large compared to r bo2 , the precedent equation can simplify as follows: () () () ?? ? ?? ??+ ?? ?? , 2 , 2 1 in rms boh bo bo bo th in rms bol v ri v v details of operation of the circuitry for brown ? out detection in nominal operation, the voltage applied to pin 7 must be higher than the 1 v internal voltage reference. in this case, the output of the comparator bo ? comp (v bo ? comp ) is low (see figure 21). conversely, if v bo goes below 1 v, v bo ? comp turns high and a 980 mv voltage source is connected to the bo pin to maintain the pin level near 1 v. the high state of v bo ? comp is used to detect a brown ? out condition. however, the brown ? out detection is not immediate. first, as soon as a high level occurs, this information is stored by a latch (l bo of figure 21) and a 500 ms delay is activated. no bo fault can be detected until this time has elapsed. the main goal of the 500 ms lag is to help meet the hold ? up requirements. in case of a short mains interruption, no fault is detected and hence, the ?pfcok? signal remains high and does not disable the downstream converter. in addition, the bo pin voltage being kept at 980 mv, there is almost no extra delay between the line recovery and the occurrence of the steady state v bo voltage, which otherwise would exist because of the large capacitor typically placed between pin7 and ground to filter the input voltage ripple. as a result, the ncp1632 effectively ?blanks? any mains interruption that is shorter than 380 ms (minimum guaranteed value of the 500 ms timer). at the end of this 500 ms blanking delay, another timer is activated that sets a 50 ms window during which a fault can be detected. this is the role of the second 500 ms timer of figure 21: ? if the output of opamp is high at the end of the first delay (500 ms blanking time) and before the second 50 ms delay time is elapsed, a brown ? out fault is detected (bo_nok is high).
ncp1632 www. onsemi.com 23 ? if the output of opamp remains low for the duration of the second delay, no fault is detected. in any case, the l bo latch and the two delays are reset at the end of the second delay. when the ?bo_nok? signal is high, the driver is disabled, the ?v control ? pin is grounded to recover operation with a soft ? start when the fault has gone and the ?pfcok? voltage turns low to disable the downstream converter. in addition, the 500 ms and 50 ms timers are reset, the 980 mv clamp is removed ( s 2 is off) and i bo , the 7 a current source, is enabled to lower the pin7 voltage for hysteresis purpose (as explained above). a pnp transistor ensures that the bo pin voltage remains below the 1 v threshold until v cc reaches v cc ( on ) . this is to guarantee that the circuit starts operation in the right state, that is, ?bonok? high. when v cc exceeds v cc ( on ) , the pnp transistor turns off and the circuit enables the 7 a current source. the 7 a current source remains on until the bo pin voltage exceeds the 1 v bo threshold. figure 22. typical input voltage of a pfc stage thermal shutdown (tsd) an internal thermal circuitry disables the circuit gate drive and then keeps the power switch off when the junction temperature exceeds 140 c typically. the output stage is then enabled once the temperature drops below about 80 c (60 c hysteresis). the temperature shutdown keeps active as long as the circuit is not reset, that is, as long as v cc keeps higher than v cc reset. the reset action forces the tsd threshold to be the upper one (140 c). this ensures that any cold start ? up will be done with the right tsd level. under ? voltage lockout section the ncp1632 incorporates an under ? voltage lockout block to prevent the circuit from operating when the power supply is not high enough to ensure a proper operation. an uvlo comparator monitors the pin 12 voltage (v cc ) to allow the ncp1632 operation when v cc exceeds 12 v typically. the comparator incorporates some hysteresis (2.0 v typically) to prevent erratic operation as the v cc crosses the threshold. when v cc goes below the uvlo comparator lower threshold, the circuit turns off. the circuit off state consumption is very low: < 50 a. this low consumption enables to use resistors to charge the v cc capacitor during the start ? up without the penalty of a too high dissipation. output drive section the circuit embeds two drivers to control the two interleaved branches. each output stage contains a totem pole optimized to minimize the cross conduction current during high frequency operation. the gate drive is kept in a sinking mode whenever the under ? voltage lockout (uvlo) is active or more generally whenever the circuit is off. its high current capability ( ? 500 ma/+800 ma) allows it to effectively drive high gate charge power mosfet. reference section the circuit features an accurate internal reference voltage (v ref ). v ref is optimized to be 2.4% accurate over the temperature range (the typical value is 2.5 v). v ref is the voltage reference used for the regulation and the over ? voltage protection. the circuit also incorporates a precise current reference (i ref ) that allows the over ? current limitation to feature a 6% accuracy over the temperature range. fault mode the following block details the function.
ncp1632 www. onsemi.com 24 figure 23. fault management block vdd regul vcc internal thermal shutdown tsd off uvlo stdwn iref irt_low (ipin3 < 7 a) vcc_ok vref fault management uvp 12 v / 10 v bo_nok r s q 30 ? s blanking time rt(open) the circuit detects a fault if the r t pin is open. practically, if the pin sources less than 7 a, the ?i rt_low ? signal sets a latch that turns off the circuit if its output (r t(open) ) is high. a 30 s blanking time avoids parasitic fault detections. the latch is reset when the circuit is in uvlo state (too low v cc levels for proper operation). when any of the following faults is detected: ? brown ? out (?bo_nok?) ? under ? voltage protection (?uvp?) ? latch ? off condition (?stdwn?) ? die over ? temperature (?tsd?) ? too low the current sourced by the r t pin (?r t(open) ?) ? ?uvlo? (improper vcc level for operation) the circuit turns off. it recovers operation when the fault disappears.
ncp1632 www. onsemi.com 25 package dimensions soic ? 16 case 751b ? 05 issue k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 18 16 9 seating plane f j m r x 45 g 8 pl p ? b ? ? a ? m 0.25 (0.010) b s ? t ? d k c 16 pl s b m 0.25 (0.010) a s t dim min max min max inches millimeters a 9.80 10.00 0.386 0.393 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.229 0.244 r 0.25 0.50 0.010 0.019 6.40 16x 0.58 16x 1.12 1.27 dimensions: millimeters 1 pitch soldering footprint 16 89 8x on semiconductor and are trademarks of semiconductor components industries, llc dba on semiconductor or its subsidiaries i n the united states and/or other countries. on semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property . a listing of on semiconductor?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent ? marking.pdf . on semiconductor reserves the right to make changes without further notice to any products herein. on semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does o n semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. buyer is responsible for its products and applications using on semiconductor products, including compliance with all laws, reg ulations and safety requirements or standards, regardless of any support or applications information provided by on semiconductor. ?typical? parameters which may be provided in on semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typic als? must be validated for each customer application by customer?s technical experts. on semiconductor does not convey any license under its patent rights nor the right s of others. on semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any fda class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. should buyer purchase or use on semicondu ctor products for any such unintended or unauthorized application, buyer shall indemnify and hold on semiconductor and its officers, employees, subsidiaries, affiliates , and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or dea th associated with such unintended or unauthorized use, even if such claim alleges that on semiconductor was negligent regarding the design or manufacture of the part. on semicon ductor is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 ncp1632/d literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc a sales representative ?

▲Up To Search▲

Price & Availability of NCP1632DR2G

	To Download NCP1632DR2G Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .